The present invention relates to frequency divider circuits, and in particular, to circuits and methods for dividing frequency by an odd value.
Clock dividers provide alternate clock sources for digital systems. A clock divider typically receives a main clock having a frequency (f1) from a central oscillator and divides the main clock frequency to produce a lower frequency (f2) based on a divisor (e.g., the number used to divide the clock). The input and output frequencies may be related as follows:
      f    ⁢                  ⁢    2    =            f      ⁢                          ⁢      1        N  where N is the divisor and may be an integer, for example.
In a synchronous system, clock signals typically have a 50% duty cycle. Accordingly, dividing a clock signal by an even value, such as N=2, 4, 6, etc. . . . , is a simple task. For example, a simple divide-by-two circuit may use a D flip flop with an output connected to the D input. If the D flip flop is triggered by the rising edge of the clock signal, the output of the D flip flop transitions at one-half the rate of the clock signal. Multiple D flip flops may be cascaded to implement other even valued dividers.
However, odd value dividers are not straightforward to implement. One existing approach to implementing odd value division uses a phase locked loop to provide high quality clock sources at lower frequencies. However, clock dividers based on phase locked loops may require a settling time when powered up or when changing divisors. If an odd value division of a clock signal is required to operate a system (e.g., during startup), such a system may take a much greater time to transition into normal operation due to this settling time.
Thus, it would be desirable to provide improved frequency divider circuits. The present invention solves these and other problems by providing circuits and methods for dividing frequency by an odd value.